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Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

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yuri-panchul/yrv-plus

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yrv

This RISC-V implementation is described in the book "Inside An Open-Source Processor" ISBN 978-3-89576-443-1

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Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

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  • Verilog 90.6%
  • SystemVerilog 4.0%
  • Shell 3.5%
  • Tcl 1.8%
  • Other 0.1%