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$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */
enhancement
New feature or request
#268
opened Apr 13, 2024 by
FPGAEveryday
Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram
enhancement
New feature or request
#267
opened Apr 8, 2024 by
rob-ng15
uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board
#254
opened Aug 19, 2023 by
at91rm9200
Many boards share a common set of features, yet each board has its own define
discussion
#246
opened Mar 5, 2023 by
sylefeb
Combinational loops may be wrongly detected when passing entire groups as parameters
enhancement
New feature or request
#237
opened Nov 5, 2022 by
sylefeb
Able to read and use inputs to algorithms, but not pass same to other algorithms
enhancement
New feature or request
#202
opened Dec 20, 2021 by
rob-ng15
Algorithm inputs not allowed as circuit outputs
enhancement
New feature or request
#201
opened Dec 4, 2021 by
rob-ng15
Special case of autorun algorithms with a single while (1) loop
enhancement
New feature or request
#184
opened Sep 16, 2021 by
sylefeb
Allow passing synthesis custom options on Makefile command line
enhancement
New feature or request
#182
opened Sep 16, 2021 by
sylefeb
Allowing always_before and always_after blocks inline
discussion
#181
opened Sep 14, 2021 by
sylefeb
hdmi.ice and subcomponents lead to unstable display
bug
Something isn't working
#170
opened Aug 20, 2021 by
rob-ng15
Issue error on clearly incorrect trackers
enhancement
New feature or request
#168
opened Aug 4, 2021 by
sylefeb
Cleanup and reorganize projects/common
enhancement
New feature or request
#165
opened Jul 19, 2021 by
sylefeb
Reset signal is pruned from algorithm with no FSM but designer may still want it
enhancement
New feature or request
#147
opened Jun 18, 2021 by
sylefeb
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