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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 244

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 752 165

  3. riscv-arch-test riscv-arch-test Public

    Assembly 545 221

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 391 96

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 318 92

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 175 53

Repositories

Showing 10 of 34 repositories
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security’s past year of commit activity
    Makefile 19 CC-BY-4.0 4 0 0 Updated Mar 17, 2025
  • riscv-ras-eri Public

    The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…

    riscv-non-isa/riscv-ras-eri’s past year of commit activity
    TeX 9 CC-BY-4.0 6 1 2 Updated Mar 16, 2025
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 108 CC-BY-4.0 18 0 4 Updated Mar 14, 2025
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc’s past year of commit activity
    Python 752 CC-BY-4.0 165 57 24 Updated Mar 14, 2025
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,488 CC-BY-4.0 244 6 9 Updated Mar 13, 2025
  • riscv-rpmi Public

    RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

    riscv-non-isa/riscv-rpmi’s past year of commit activity
    Makefile 10 CC-BY-4.0 9 1 0 Updated Mar 13, 2025
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 30 CC-BY-4.0 17 2 2 Updated Mar 13, 2025
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    Makefile 26 CC-BY-4.0 7 1 1 Updated Mar 12, 2025
  • riscv-acpi-rimt Public

    RISC-V ACPI I/O Mapping Table Specification

    riscv-non-isa/riscv-acpi-rimt’s past year of commit activity
    Makefile 4 CC-BY-4.0 3 0 0 Updated Mar 12, 2025
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 175 CC-BY-4.0 53 29 9 Updated Mar 11, 2025
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