List of awesome semiconductor startups

An Open Source Link Protocol and Controller

VeeR EL2 Core

VeeR EH1 core

CoreScore

cocotb: Python-based chip (RTL) verification

SERV - The SErial RISC-V CPU

GCC port for OpenRISC 1000

OpenRISC toolchain build scripts

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Package manager and build abstraction tool for FPGA/ASIC development

mor1kx - an OpenRISC 1000 processor IP core

CGEN

binutils with cleaned up OpenRISC port based on CGEN-based opcodes and gas libraries

Disassembly and execution trace generation library for OpenRISC 1000 models