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Created pipelined, 32-bit processing core; can fetch, decode, and execute 16 unique instructions; complete with hazard, bypassing, and stall logic.

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belaltaher8/Pipelined-Processor

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db
db
 
 
greybox_tmp
greybox_tmp
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
simulation
simulation
 
 
.gitattributes
.gitattributes
 
 
.gitignore
.gitignore
 
 
ALUtest.PNG
ALUtest.PNG
 
 
Decode1.jpg
Decode1.jpg
 
 
Decode2.jpg
Decode2.jpg
 
 
Execute.jpg
Execute.jpg
 
 
ExecuteBypassing.jpg
ExecuteBypassing.jpg
 
 
Fetch.jpg
Fetch.jpg
 
 
HierarchicalCarryLookaheadAdder.PNG
HierarchicalCarryLookaheadAdder.PNG
 
 
MemBypassing.jpg
MemBypassing.jpg
 
 
Memory.jpg
Memory.jpg
 
 
PipelinedProcessorISA.PNG
PipelinedProcessorISA.PNG
 
 
Processor.jpg
Processor.jpg
 
 
ProcessorTechnicalReport.tex
ProcessorTechnicalReport.tex
 
 
README.md
README.md
 
 
RegFile.JPG
RegFile.JPG
 
 
Waveform.vwf
Waveform.vwf
 
 
Write.jpg
Write.jpg
 
 
alu.v
alu.v
 
 
alu.v.bak
alu.v.bak
 
 
bexTest.PNG
bexTest.PNG
 
 
bexTest2.PNG
bexTest2.PNG
 
 
bltTest.PNG
bltTest.PNG
 
 
bltTest2.PNG
bltTest2.PNG
 
 
bneTest.PNG
bneTest.PNG
 
 
bneTest2.PNG
bneTest2.PNG
 
 
dflipflop.v
dflipflop.v
 
 
dflipflop.v.bak
dflipflop.v.bak
 
 
dmem.mif
dmem.mif
 
 
dmem.qip
dmem.qip
 
 
dmem.v
dmem.v
 
 
dmem_bb.v
dmem_bb.v
 
 
imem.mif
imem.mif
 
 
imem.mif.bak
imem.mif.bak
 
 
imem.qip
imem.qip
 
 
imem.v
imem.v
 
 
imem_bb.v
imem_bb.v
 
 
jaljrTest.PNG
jaljrTest.PNG
 
 
my_12bit2to1_mux.v
my_12bit2to1_mux.v
 
 
my_12bit_register.v
my_12bit_register.v
 
 
my_12bit_register.v.bak
my_12bit_register.v.bak
 
 
my_12to32bit_extender.v
my_12to32bit_extender.v
 
 
my_12to32bit_extender.v.bak
my_12to32bit_extender.v.bak
 
 
my_12tri.v
my_12tri.v
 
 
my_16bit_leftshifter.v
my_16bit_leftshifter.v
 
 
my_16bit_rightshifter.v
my_16bit_rightshifter.v
 
 
my_17to32bit_extender.v
my_17to32bit_extender.v
 
 
my_1bit_full_adder.v
my_1bit_full_adder.v
 
 
my_1bit_leftshifter.v
my_1bit_leftshifter.v
 
 
my_1bit_rightshifter.v
my_1bit_rightshifter.v
 
 
my_1bit_xor.v
my_1bit_xor.v
 
 
my_2bit_leftshifter.v
my_2bit_leftshifter.v
 
 
my_2bit_rightshifter.v
my_2bit_rightshifter.v
 
 
my_2to1_mux.v
my_2to1_mux.v
 
 
my_2to4_decoder.v
my_2to4_decoder.v
 
 
my_32bit16to1_mux.v
my_32bit16to1_mux.v
 
 
my_32bit16to1_mux.v.bak
my_32bit16to1_mux.v.bak
 
 
my_32bit2to1_mux.v
my_32bit2to1_mux.v
 
 
my_32bit32to1_mux.v
my_32bit32to1_mux.v
 
 
my_32bit4to1_mux.v
my_32bit4to1_mux.v
 
 
my_32bit4to1_mux.v.bak
my_32bit4to1_mux.v.bak
 
 
my_32bit8to1_mux.v
my_32bit8to1_mux.v
 
 
my_32bit8to1_mux.v.bak
my_32bit8to1_mux.v.bak
 
 
my_32bit_barrelLeftShifter.v
my_32bit_barrelLeftShifter.v
 
 
my_32bit_barrelRightShifter.v
my_32bit_barrelRightShifter.v
 
 
my_32bit_register.v
my_32bit_register.v
 
 
my_32bit_register.v.bak
my_32bit_register.v.bak
 
 
my_32tri.v
my_32tri.v
 
 
my_3to8_decoder.v
my_3to8_decoder.v
 
 
my_4bit_leftshifter.v
my_4bit_leftshifter.v
 
 
my_4bit_rightshifter.v
my_4bit_rightshifter.v
 
 
my_5bit2to1_mux.v
my_5bit2to1_mux.v
 
 
my_5bit2to1_mux.v.bak
my_5bit2to1_mux.v.bak
 
 
my_5bit4to1_mux.v
my_5bit4to1_mux.v
 
 
my_5bit4to1_mux.v.bak
my_5bit4to1_mux.v.bak
 
 
my_5bit_comparator.v
my_5bit_comparator.v
 
 
my_5bit_comparator.v.bak
my_5bit_comparator.v.bak
 
 
my_5bit_register.v
my_5bit_register.v
 
 
my_5bit_register.v.bak
my_5bit_register.v.bak
 
 
my_5to32_decoder.v
my_5to32_decoder.v
 
 
my_8bit_leftshifter.v
my_8bit_leftshifter.v
 
 
my_8bit_rightshifter.v
my_8bit_rightshifter.v
 
 
my_ALU_adder.v
my_ALU_adder.v
 
 
my_ALU_adder.v.bak
my_ALU_adder.v.bak
 
 
my_CLA_full_adder.v
my_CLA_full_adder.v
 
 
my_bitwise_and.v
my_bitwise_and.v
 
 
my_bitwise_or.v
my_bitwise_or.v
 
 
my_c16.v
my_c16.v
 
 
my_c24.v
my_c24.v
 
 
my_c32.v
my_c32.v
 
 
my_c8.v
my_c8.v
 
 
my_tri.v
my_tri.v
 
 
processor.qpf
processor.qpf
 
 
processor.qsf
processor.qsf
 
 
processor.qws
processor.qws
 
 

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Pipelined-Processor

This repository contains a fully-functional 32-bit pipelined processor core created using Quartus Prime.

The repository includes:

  • Program Counter
  • Instruction Memory
  • Register File
  • Arithmetic-Logic Unit
  • Data Memory
  • Stall Logic
  • Bypassing Logic for both Execute and Memory
  • Hazard Detection
  • 30+ Page technical report with illustrations and implementation/interface details
  • Waveform diagrams from Quartus Prime illustrating processor functionality

Processor

Processor

Instruction Set

ISA

Fetch

Fetch

Decode

Decode1 Decode2

Execute

Execute

Execute Bypassing

ExecuteBypassing

Memory

Memory

Memory Bypassing

MemBypassing

Write

Processor

About

Created pipelined, 32-bit processing core; can fetch, decode, and execute 16 unique instructions; complete with hazard, bypassing, and stall logic.

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