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Verification-of-UART-communication-protocol-design-using-System-Verilog
Verification-of-UART-communication-protocol-design-using-System-Verilog Public -
Vending-Machine-FPGA-SYNTHESISABLE
Vending-Machine-FPGA-SYNTHESISABLE PublicThis is a classic example of how to apply theoretical knowlegde to some practical application .In this project I have made a vending machine by implementing it's state diagram as a Verilog code and…
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generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder
generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder Public -
-Verifying-4-bit-Multiplier-design-using-System-Verilog
-Verifying-4-bit-Multiplier-design-using-System-Verilog Public
5 contributions in the last year
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Contribution activity
March 2025
Created 3 commits in 2 repositories
Created 2 repositories
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Akul-Verma/solar-power-generation-System-f...
This contribution was made on Mar 5
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Akul-Verma/Calculator-Using-Arduino-UNO
This contribution was made on Mar 4