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partial implementation for SIMD_WIDTH and collector units
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@tinebp
tinebp committed Feb 18, 2025
1 parent 9072ec4 commit e9c9678
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Showing 104 changed files with 2,489 additions and 2,111 deletions.
22 changes: 10 additions & 12 deletions hw/rtl/VX_cluster.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ module VX_cluster import VX_gpu_pkg::*; #(

`ifdef SCOPE
localparam scope_socket = 0;
`SCOPE_IO_SWITCH (`NUM_SOCKETS);
`SCOPE_IO_SWITCH (NUM_SOCKETS);
`endif

`ifdef PERF_ENABLE
Expand All @@ -53,12 +53,12 @@ module VX_cluster import VX_gpu_pkg::*; #(

`ifdef GBAR_ENABLE

VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
VX_gbar_bus_if per_socket_gbar_bus_if[NUM_SOCKETS]();
VX_gbar_bus_if gbar_bus_if();

VX_gbar_arb #(
.NUM_REQS (`NUM_SOCKETS),
.OUT_BUF ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
.NUM_REQS (NUM_SOCKETS),
.OUT_BUF ((NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
) gbar_arb (
.clk (clk),
.reset (reset),
Expand All @@ -79,7 +79,7 @@ module VX_cluster import VX_gpu_pkg::*; #(
VX_mem_bus_if #(
.DATA_SIZE (`L1_LINE_SIZE),
.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
) per_socket_mem_bus_if[`NUM_SOCKETS * `L1_MEM_PORTS]();
) per_socket_mem_bus_if[NUM_SOCKETS * `L1_MEM_PORTS]();

`RESET_RELAY (l2_reset, reset);

Expand All @@ -101,8 +101,6 @@ module VX_cluster import VX_gpu_pkg::*; #(
.WRITEBACK (`L2_WRITEBACK),
.DIRTY_BYTES (`L2_DIRTYBYTES),
.REPL_POLICY (`L2_REPL_POLICY),
.UUID_WIDTH (`UUID_WIDTH),
.FLAGS_WIDTH (`MEM_REQ_FLAGS_WIDTH),
.CORE_OUT_BUF (3),
.MEM_OUT_BUF (3),
.NC_ENABLE (1),
Expand All @@ -119,19 +117,19 @@ module VX_cluster import VX_gpu_pkg::*; #(

///////////////////////////////////////////////////////////////////////////

wire [`NUM_SOCKETS-1:0] per_socket_busy;
wire [NUM_SOCKETS-1:0] per_socket_busy;

// Generate all sockets
for (genvar socket_id = 0; socket_id < `NUM_SOCKETS; ++socket_id) begin : g_sockets
for (genvar socket_id = 0; socket_id < NUM_SOCKETS; ++socket_id) begin : g_sockets

`RESET_RELAY (socket_reset, reset);

VX_dcr_bus_if socket_dcr_bus_if();
wire is_base_dcr_addr = (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, dcr_bus_if, is_base_dcr_addr, (`NUM_SOCKETS > 1))
`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, dcr_bus_if, is_base_dcr_addr, (NUM_SOCKETS > 1))

VX_socket #(
.SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + socket_id),
.SOCKET_ID ((CLUSTER_ID * NUM_SOCKETS) + socket_id),
.INSTANCE_ID (`SFORMATF(("%s-socket%0d", INSTANCE_ID, socket_id)))
) socket (
`SCOPE_IO_BIND (scope_socket+socket_id)
Expand All @@ -155,6 +153,6 @@ module VX_cluster import VX_gpu_pkg::*; #(
);
end

`BUFFER_EX(busy, (| per_socket_busy), 1'b1, 1, (`NUM_SOCKETS > 1));
`BUFFER_EX(busy, (| per_socket_busy), 1'b1, 1, (NUM_SOCKETS > 1));

endmodule
179 changes: 96 additions & 83 deletions hw/rtl/VX_config.vh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,18 +114,6 @@
`define SOCKET_SIZE `MIN(4, `NUM_CORES)
`endif

`ifdef L2_ENABLE
`define L2_ENABLED 1
`else
`define L2_ENABLED 0
`endif

`ifdef L3_ENABLE
`define L3_ENABLED 1
`else
`define L3_ENABLED 0
`endif

`ifdef L1_DISABLE
`define ICACHE_DISABLE
`define DCACHE_DISABLE
Expand Down Expand Up @@ -247,18 +235,10 @@
`ifndef IO_MPM_ADDR
`define IO_MPM_ADDR (`IO_COUT_ADDR + `IO_COUT_SIZE)
`endif
`define IO_MPM_SIZE (8 * 32 * `NUM_CORES * `NUM_CLUSTERS)

`ifndef STACK_LOG2_SIZE
`define STACK_LOG2_SIZE 13
`endif
`define STACK_SIZE (1 << `STACK_LOG2_SIZE)

`define RESET_DELAY 8

`ifndef STALL_TIMEOUT
`define STALL_TIMEOUT (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED)))
`endif

`ifndef SV_DPI
`ifndef DPI_DISABLE
Expand Down Expand Up @@ -296,95 +276,105 @@
`ifndef MEM_PAGE_SIZE
`define MEM_PAGE_SIZE (4096)
`endif

`ifndef MEM_PAGE_LOG2_SIZE
`define MEM_PAGE_LOG2_SIZE (12)
`endif

// Virtual Memory Configuration ///////////////////////////////////////////////

`ifdef VM_ENABLE
`ifdef XLEN_32
`ifndef VM_ADDR_MODE
`define VM_ADDR_MODE SV32 //or BARE
`endif
`ifndef PT_LEVEL
`define PT_LEVEL (2)
`endif
`ifndef PTE_SIZE
`define PTE_SIZE (4)
`endif
`ifndef NUM_PTE_ENTRY
`define NUM_PTE_ENTRY (1024)
`endif
`ifndef PT_SIZE_LIMIT
`define PT_SIZE_LIMIT (1<<23)
`endif
`else
`ifndef VM_ADDR_MODE
`define VM_ADDR_MODE SV39 //or BARE
`endif
`ifndef PT_LEVEL
`define PT_LEVEL (3)
`endif
`ifndef PTE_SIZE
`define PTE_SIZE (8)
`endif
`ifndef NUM_PTE_ENTRY
`define NUM_PTE_ENTRY (512)
`endif
`ifndef PT_SIZE_LIMIT
`define PT_SIZE_LIMIT (1<<25)
`endif
`ifdef XLEN_32
`ifndef VM_ADDR_MODE
`define VM_ADDR_MODE SV32 //or BARE
`endif

`ifndef PT_SIZE
`define PT_SIZE MEM_PAGE_SIZE
`ifndef PT_LEVEL
`define PT_LEVEL (2)
`endif

`ifndef TLB_SIZE
`define TLB_SIZE (32)
`ifndef PTE_SIZE
`define PTE_SIZE (4)
`endif
`ifndef NUM_PTE_ENTRY
`define NUM_PTE_ENTRY (1024)
`endif
`ifndef PT_SIZE_LIMIT
`define PT_SIZE_LIMIT (1<<23)
`endif
`else
`ifndef VM_ADDR_MODE
`define VM_ADDR_MODE SV39 //or BARE
`endif
`ifndef PT_LEVEL
`define PT_LEVEL (3)
`endif
`ifndef PTE_SIZE
`define PTE_SIZE (8)
`endif
`ifndef NUM_PTE_ENTRY
`define NUM_PTE_ENTRY (512)
`endif
`ifndef PT_SIZE_LIMIT
`define PT_SIZE_LIMIT (1<<25)
`endif
`endif

`ifndef PT_SIZE
`define PT_SIZE MEM_PAGE_SIZE
`endif

`ifndef TLB_SIZE
`define TLB_SIZE (32)
`endif
`endif

// Pipeline Configuration /////////////////////////////////////////////////////

`ifndef SIMD_WIDTH
`define SIMD_WIDTH `MAX(`NUM_THREADS, 16)
`define SIMD_WIDTH `MIN(`NUM_THREADS, 2)
`endif

// Issue width
`ifndef ISSUE_WIDTH
`define ISSUE_WIDTH `UP(`NUM_WARPS / 8)
`endif

// Operand collectors
`ifndef NUM_OPCS
`define NUM_OPCS 4
`endif

// Register File Banks
`ifndef NUM_GPR_BANKS
`define NUM_GPR_BANKS `MIN(`NUM_OPCS, 4)
`endif

// Number of ALU units
`ifndef NUM_ALU_LANES
`define NUM_ALU_LANES `NUM_THREADS
`define NUM_ALU_LANES `SIMD_WIDTH
`endif
`ifndef NUM_ALU_BLOCKS
`define NUM_ALU_BLOCKS `ISSUE_WIDTH
`endif

// Number of FPU units
`ifndef NUM_FPU_LANES
`define NUM_FPU_LANES `NUM_THREADS
`define NUM_FPU_LANES `SIMD_WIDTH
`endif
`ifndef NUM_FPU_BLOCKS
`define NUM_FPU_BLOCKS `ISSUE_WIDTH
`endif

// Number of LSU units
`ifndef NUM_LSU_LANES
`define NUM_LSU_LANES `NUM_THREADS
`define NUM_LSU_LANES `SIMD_WIDTH
`endif
`ifndef NUM_LSU_BLOCKS
`define NUM_LSU_BLOCKS 1
`endif

// Number of SFU units
`ifndef NUM_SFU_LANES
`define NUM_SFU_LANES `NUM_THREADS
`define NUM_SFU_LANES `SIMD_WIDTH
`endif
`ifndef NUM_SFU_BLOCKS
`define NUM_SFU_BLOCKS 1
Expand All @@ -402,20 +392,14 @@

// Size of LSU Core Request Queue
`ifndef LSUQ_IN_SIZE
`define LSUQ_IN_SIZE (2 * (`NUM_THREADS / `NUM_LSU_LANES))
`define LSUQ_IN_SIZE (2 * (`SIMD_WIDTH / `NUM_LSU_LANES))
`endif

// Size of LSU Memory Request Queue
`ifndef LSUQ_OUT_SIZE
`define LSUQ_OUT_SIZE `MAX(`LSUQ_IN_SIZE, `LSU_LINE_SIZE / (`XLEN / 8))
`endif

`ifdef GBAR_ENABLE
`define GBAR_ENABLED 1
`else
`define GBAR_ENABLED 0
`endif

`ifndef LATENCY_IMUL
`ifdef VIVADO
`define LATENCY_IMUL 4
Expand All @@ -432,7 +416,7 @@

// Size of FPU Request Queue
`ifndef FPUQ_SIZE
`define FPUQ_SIZE (2 * (`NUM_THREADS / `NUM_FPU_LANES))
`define FPUQ_SIZE (2 * (`SIMD_WIDTH / `NUM_FPU_LANES))
`endif

// FNCP Latency
Expand Down Expand Up @@ -545,10 +529,8 @@
`ifndef ICACHE_DISABLE
`define ICACHE_ENABLE
`endif
`ifdef ICACHE_ENABLE
`define ICACHE_ENABLED 1
`else
`define ICACHE_ENABLED 0

`ifndef ICACHE_ENABLE
`define NUM_ICACHES 0
`endif

Expand Down Expand Up @@ -602,10 +584,8 @@
`ifndef DCACHE_DISABLE
`define DCACHE_ENABLE
`endif
`ifdef DCACHE_ENABLE
`define DCACHE_ENABLED 1
`else
`define DCACHE_ENABLED 0

`ifndef DCACHE_ENABLE
`define NUM_DCACHES 0
`define DCACHE_NUM_BANKS 1
`endif
Expand Down Expand Up @@ -680,10 +660,7 @@
`define LMEM_ENABLE
`endif

`ifdef LMEM_ENABLE
`define LMEM_ENABLED 1
`else
`define LMEM_ENABLED 0
`ifndef LMEM_ENABLE
`define LMEM_NUM_BANKS 1
`endif

Expand Down Expand Up @@ -816,6 +793,42 @@

// ISA Extensions /////////////////////////////////////////////////////////////

`ifdef ICACHE_ENABLE
`define ICACHE_ENABLED 1
`else
`define ICACHE_ENABLED 0
`endif

`ifdef DCACHE_ENABLE
`define DCACHE_ENABLED 1
`else
`define DCACHE_ENABLED 0
`endif

`ifdef LMEM_ENABLE
`define LMEM_ENABLED 1
`else
`define LMEM_ENABLED 0
`endif

`ifdef GBAR_ENABLE
`define GBAR_ENABLED 1
`else
`define GBAR_ENABLED 0
`endif

`ifdef L2_ENABLE
`define L2_ENABLED 1
`else
`define L2_ENABLED 0
`endif

`ifdef L3_ENABLE
`define L3_ENABLED 1
`else
`define L3_ENABLED 0
`endif

`ifdef EXT_A_ENABLE
`define EXT_A_ENABLED 1
`else
Expand Down
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