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Issues list

document constraints API improvement
#76 opened Aug 23, 2017 by jordens
Missing documentation for migen.genlib modules improvement
#23 opened Jul 2, 2015 by mithro
1 of 12 tasks
1
Migen Namer __main__ Decoration fixed-in-nmigen improvement
#29 opened Aug 25, 2015 by cr1901
4
incorrect Cat element width in Verilog export bug fixed-in-nmigen
#33 opened Oct 19, 2015 by sbourdeauducq
Records with 0 fields generate invalid verilog bug fixed-in-nmigen
#41 opened Mar 17, 2016 by nakengelhardt
4
FullMemoryWE and SplitMemory break direct access to memory in simulation fixed-in-nmigen improvement
#53 opened Nov 15, 2016 by jordens
1
constrain CDCs with max_delay [vivado] fixed-in-nmigen improvement
#58 opened Nov 22, 2016 by jordens
1
support asymmetric dual-port memories feature
#61 opened Dec 4, 2016 by sbourdeauducq
1
consider removing the depth parameter of ElasticBuffer question
#63 opened Jan 13, 2017 by sbourdeauducq
@enjoy-digital
1
construct and use sensitivity graph to speed up sim and find comb loops fixed-in-nmigen improvement
#69 opened Jun 9, 2017 by jordens
2
export as hierarchy (verilog modules) feature fixed-in-nmigen
#70 opened Jun 19, 2017 by jordens
6
AsyncFIFO reset fixed-in-nmigen improvement
#73 opened Jul 2, 2017 by jordens
2
migen travis config should push development versions to PyPi improvement
#17 opened Apr 20, 2015 by mithro
@fallen
1
sim/verilog mismatch: mux bug fixed-in-nmigen
#75 opened Jul 17, 2017 by jordens
document platform, toolchain API and build process hooks improvement
#77 opened Aug 23, 2017 by jordens
tutorial out of date (was: Issue with importing Signal) bug
#80 opened Oct 10, 2017 by sheeets
3
redesign platform resource feature improvement
#82 opened Oct 28, 2017 by jordens
3
make post-synthesis results compatible with Vivado GUI feature
#99 opened Jan 18, 2018 by sbourdeauducq
1
Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?) fixed-in-nmigen question
#102 opened Feb 14, 2018 by mithro
23
mark proper CDCs as such, use to flag CDC errors and to emit timing exceptions automatically feature improvement
#103 opened Mar 7, 2018 by jordens
dual-port, writable, READ_FIRST, memory pattern not recognized bug
#107 opened May 7, 2018 by jordens
1
chained comparisons are not implemented correctly bug fixed-in-nmigen
#108 opened May 13, 2018 by whitequark
1
Empty FSM states do not produce expected behavior bug fixed-in-nmigen
#112 opened May 28, 2018 by whitequark
1
review expression size and signedness fixed-in-nmigen improvement
#115 opened Jun 10, 2018 by jordens
1
assignment of combinatorial values with delayed assignment gives incorrect results when referencing same signal
#303 opened Mar 11, 2025 by jwise
3
ProTip! Updated in the last three days: updated:>2025-03-27.