Prune unused, unnamed module outputs when generating SV

[mkorbel1]

Motivation

If someone, for example, calls a swizzle on a bus but doesn't use the output, the result still shows up in the SystemVerilog. This isn't functionally necessary, and also is probably not wanted if it wasn't named.

Desired solution

Detect when (certain?) modules are instantiated who have no outputs used and omit them from generated SystemVerilog.

This should probably only apply to special cases, since there may be custom SystemVerilog modules where you indeed do want there to be signals left around. Maybe it should be a flag in the SystemVerilog mixin?

Alternatives considered

No response

Additional details

No response