BtGuard: VB : 0, MB : 0 ============= Intel Slim Bootloader STAGE1A ============= SBID: SB_APLI ISVN: 001 IVER: 000.005.001.000.18683 SVER: 7CD39871646A5F6D-dirty FDBG: BLD(D IA32) FSP(D) FSPV: ID($APLFSP$) REV(01040301) Loader global data @ 0xFEF71C40 Run STAGE1A @ 0xFEF00000 Load STAGE1B @ 0xFEF80000 No BtGuard verification ! ============= Intel Slim Bootloader STAGE1B ============= CPU : APL-F1 [2C @ 1300MHz: premium SKU], uCode rev.8 Early GpioInit for EMMC MMC global data init Use SDMA instead of ADMA2 MMC Phase 1 init SpiInstance = FEF7B2B0 PchSpiBase at 0x00000D02 ScSpiBar0 at 0xD2000000 Append public key hash into store: Unsupported Load EXT CFG Data @ 0xFEF7BB54:0x0CEC ... Success HASH verification for usage (0x00000200) with Hash Alg (0x1): Success SignType (0x2) SignSize (0x100) SignHashAlg (0x1) RSA verification for usage (0x00000200): Success GPIO based PID detection is disabled Get Embedded BoardId BOOT: BP0 MODE: 0 BoardID: 0x07 PlatformName: LeafHill BootPolicy : 0x00000000 Memory Init Looking for MRC saving data MRC data NOT found Load memory parameters from CfgData. Load general parameter from CfgData. Call FspMemoryInit ... ============= FSP Spec v2.0 Header Revision v3 ($APLFSP$ v1.4.3.1) ============= Fsp BootFirmwareVolumeBase - 0xFEF94000 Fsp BootFirmwareVolumeSize - 0x59000 Fsp TemporaryRamBase - 0xFEF16000 Fsp TemporaryRamSize - 0x2A000 Fsp PeiTemporaryRamBase - 0xFEF16000 Fsp PeiTemporaryRamSize - 0x1B4CC Fsp StackBase - 0xFEF314CC Fsp StackSize - 0xEB34 Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FEF94000, size is 0x00059000, handle is 0x0 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FEFA1970 EntryPoint=0x000FEFA1A40 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FEFA2FDC EntryPoint=0x000FEFA30E4 FspInitPreMem.efi Install PPI: 820695B0-C2F2-4EC7-A252-DB0DBEE838A3 Install PPI: CFE5EC91-31ED-47E9-BE7D-9CCB59134B71 Install PPI: CBD86677-362F-4C04-9459-A741326E05CF Warning: PcdIafwPlatformInfo set to Safe_Warning_Value Install PPI: 563F8EDE-1FA5-45A2-BE23-B0B6A07DE239 Loading PEIM at 0x000FEFAFD7C EntryPoint=0x000FEFAFE6C SiInitPreMem.efi SiInitPrePolicy() Start ScInitPrePolicy() - Start POSTCODE=<0000DB00> ScInitPreMem() - Start POSTCODE=<0000DB02> ScEarlyInit() - Start ScSmbusInit() Start ScSmbusInit() End ConfigureLpcOnEarlyPei() ScEarlyInit() - End POSTCODE=<0000DB7F> ScInitPreMem() - End ScInitPrePolicy() - End POSTCODE=<0000DB10> ScConfigurePciePowerSequence () PerstDelayTime = -401 ms Disabling PCIE RP 3 Pre-Mem North Cluster Entry POSTCODE=<0000DA00> PeiNpkInit() - Start NpkReserveHob->NpkPreMemConfig.NpkEn = 0x0 NpkReserveHob->NpkPreMemConfig.NpkVrcTapEn = 0x0 NpkReserveHob->NpkPreMemConfig.FwTraceEn = 0x1 NpkReserveHob->NpkPreMemConfig.RecoverDump = 0x0 NpkReserveHob->NpkPreMemConfig.FwTraceDestination = 0x4 NpkReserveHob->NpkPreMemConfig.Msc0Size = 0x0 NpkReserveHob->NpkPreMemConfig.Msc0Wrap = 0x1 NpkReserveHob->NpkPreMemConfig.Msc1Size = 0x0 NpkReserveHob->NpkPreMemConfig.Msc1Wrap = 0x1 NpkReserveHob->NpkPreMemConfig.PtiMode = 0x1 NpkReserveHob->NpkPreMemConfig.PtiTraining = 0x0 NpkReserveHob->NpkPreMemConfig.PtiSpeed = 0x2 NpkReserveHob->NpkPreMemConfig.PunitMlvl = 0x1 NpkReserveHob->NpkPreMemConfig.PmcMlvl = 0x1 NpkReserveHob->NpkPreMemConfig.SwTraceEn = 0x0 NpkReserveHob->NpkPreMemConfig.NpkDCIEn = 0x0 CSE Host_Secboot_0 value 0x0 Disable NPK by sending IPC1 message. SaPreMemConfig->RtEn 0 Initializing Pre-Mem Graphics POSTCODE=<0000DA50> iGFX initialization Start IGD enabled. GMSData: 0x2 iGFX initialization End Pre-Mem North Cluster Exit POSTCODE=<0000DA7F> SiInitPrePolicy() - End Loading PEIM at 0x000FEFB62CC EntryPoint=0x000FEFB63BC MemoryInit.efi Profile is now set to: 10 MRC SeCUmaSize memory size from SeC ... 0 BXTP-F1 detected! CPU stepping = 112. BXT Series = 3. SKPD: 0x00000000 DEBUP: 0x00000000 MRC Parameters not valid. Status is Success MRC: DRAM in SR: 0 Cold boot detected. >>> ### Rank Margin Tool Enabled on smip= [1] ### <<< CurrentBootMode -> 8 ValidFlag -> 0 NOT Restore Path Ch[0] 1 rank DIMM0 Memory Size: 1024, System Mem 1024 in MB Ch0 SLICE_0_MASTER: 1 SLICE_1_MASTER: 0 Overall ChEnMask: 0x1 LP3/LP4 ChEnMask PHY0: 0x1 PHY1: 0x0 FREQ_HIGH: 16 BootMode set to: 8 (FB=0x10; S5=8; S0=1,2,4; S3=0x20) CurrentFreq = 5 (1333 = 2, 1600 = 3, 1866 =4, 2133 = 5, 2400 = 6, 2666 = 7, 3200 = 8) SystemMemSize = 400 CH 0 Enabled LPDDR4 CP 00 MRC REVISION ID 0.56.41 + MMRC REVISION ID 89.24 DRAM Policy: ChannelHashMask :0x0 SliceHashMask :0x0 ChannelsSlicesEnabled :0x0 ScramblerSupport :0x1 InterleavedMode :0x0 MinRefRate2xEnabled :0x0 DualRankSupportEnabled :0x1 Profile :0xA SpdAddress[0] :0x0 SpdAddress[1] :0x0 SystemMemorySizeLimit :0x1800 LowMemMaxVal :0x0 HighMemMaxVal :0x0 DisableFastBoot :0x0 RmtMode :0x1 RmtCheckRun :0x0 RmtMarginCheckScaleHighThreshold:0xC8 MsgLevelMask :0x0 MemoryDown :0x1 Channel0: RankEnable :0x1 DeviceWidth :0x1 DramDensity :0x2 Option :0x3 OdtConfig :0x0 TristateClk1 :0x0 Mode2N :0x0 OdtLevels :0x0 Swizzling: 9 E C D A B 8 F 5 6 1 0 2 7 4 3 1A 1F 1C 1B 1D 19 18 1E 14 16 17 11 12 13 10 15 CP 01 FREQ_HIGH: 16 FreqHi 5 CP 02 Won't run on disabled channels MrcData::AddrMirror: 0 CASWIZZLE 1 SABy2Clk: 267; SpidClk: 267 CustomTSV: 16 CP F1 Won't run on disabled channels Speed set to:5 CP 03 CP 04 CP 05 CP 07 Forcing run on disabled channels CP 08 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 09 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 0B Won't run on disabled channels CP 10 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 11 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 12 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 13 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 14 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 15 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 16 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 17 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 18 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 19 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 20 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 21 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 22 CP 23 CP 24 CP 26 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 27 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 28 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 30 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 31 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 36 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 36 Forcing run on disabled channels CP F1 Set Boot Freq:3 Speed set to:3 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 CP 39 Ecc Disabled A0 Offset 0 CP 3C Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 3D Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 3F ClkGatePhy Ch1 disable Ch2 disable Ch3 disable CP 40 Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels Forcing run on disabled channels CP 41 Won't run on disabled channels CP F1 Speed set to:5 CP 43 CP 47 Won't run on disabled channels CP 44 CP 49 DRAM Resetting CP 4A Won't run on disabled channels CP F1 Won't run on disabled channels Set Software Init Freq:3 Speed set to:3 CP 4B Won't run on disabled channels CP 4C Won't run on disabled channels CP C0 CP 4E Won't run on disabled channels CP 4F Won't run on disabled channels CP 4F Won't run on disabled channels CP A0 Won't run on disabled channels Comp Vref Code = 4 Pull Up Ron = 140 Pull Up COMP Vref Code = 4 Pull Up RComp = 10 Pull Dn Ron = 40 Pull Dn COMP Vref Code = 41 Pull Dn RComp = 59, 59, 59 Sweeping Vref for 1->0 transition on VOCSampler holding VOC=0 VOC SL0:00:00:00:00:00:00:00:00 SL1:00:00:00:00:00:00:00:00 SL2:00:00:00:00:00:00:00:00 SL3:00:00:00:00:00:00:00:00 VREF SL0:08:11:10:11:13:13:12:11[10] SL1:13:13:10:13:13:13:16:11[13] SL2:12:13:15:17:17:12:09:11[13] SL3:13:13:11:09:12:18:14:11[13] 00 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 01 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 02 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 03 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 04 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 05 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:1:1: 1:1:1:1:1:1:0:1: 1:1:1:0:1:1:1:1: 06 0:1:1:1:1:1:1:1: 1:1:0:1:1:1:1:0: 0:1:1:1:1:1:0:0: 1:1:0:0:1:1:1:0: 07 0:1:0:1:1:1:1:1: 0:0:0:0:1:0:1:0: 0:0:1:1:1:0:0:0: 0:0:0:0:0:1:1:0: 08 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 09 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 10 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 11 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 12 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 13 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 14 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 15 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: 0:0:0:0:0:0:0:0: Resetting Voc to 0 Resetting Voc to 0 Resetting Voc to 0 Resetting Voc to 0 Sweeping Vref for 1->0 transition on VOCSampler with VOC Normalized. VOC SL0:06:08:07:08:08:08:08:08 SL1:07:07:06:07:07:07:08:06 SL2:07:07:08:08:08:07:06:06 SL3:07:07:06:05:07:08:08:06 VREF SL0:10:07:10:07:08:08:07:06[08] SL1:14:13:12:13:13:13:13:13[13] SL2:12:13:11:13:13:12:12:13[12] SL3:12:13:13:12:12:13:10:13[11] CP 50 Won't run on disabled channels CP 51 Won't run on disabled channels CP F1 Speed set to:5 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 CP A2 Won't run on disabled channels Channel 0, Rank 0 Control value 100 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 124 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 148 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 172 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 196 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 220 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 244 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 268 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- Control value 292 S00K0 ECT: S00000000, E33003300 CH00 0102:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0294:- ECT: S00000000, E33003300 CH00 0270:- ECT: S00000000, E33003300 CH00 0246:- ECT: S00000000, E33003300 CH00 0222:- ECT: S00000000, E33003300 CH00 0198:- ECT: S00000000, E33003300 CH00 0174:- ECT: S00000000, E33003300 CH00 0150:- ECT: S00000000, E33003300 CH00 0126:- ECT: S00000000, E33003300 CH00 0102:- ERROR: Highest Value found is a 0 Final solution Rank 0 = 0, 0, Final control is 100, Final command is 102 CP 56 Won't run on disabled channels CP B2 DRAM Resetting Set Boot Freq:3 Speed set to:3 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 DefaultCmdClkCtl=1 Speed set to:5 TimingParam nWR = 24, MR1 = 36046 Speed set to:5 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 Speed set to:5 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 Speed set to:5 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 Speed set to:5 Ecc Disabled A0 Offset 0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 DefaultCmdClkCtl=0 CP 69 Won't run on disabled channels CP 6A Won't run on disabled channels CP A5 Won't run on disabled channels C00R0 Initial Delay Value=1248 Detect Rising Edge Large, Step=25, dithering=0 S00K0 S01K0 S02K0 S03K0 CH00 1248:- 1248:- 1248:- 1248:- CH00 1273:- 1273:- 1273:- 1273:- CH00 1298:- 1298:- 1298:- 1298:- CH00 1323:- 1323:- 1323:- 1323:- CH00 1348:- 1348:- 1348:- 1348:- CH00 1373:- 1373:- 1373:- 1373:- CH00 1398:- 1398:- 1398:- 1398:- CH00 1423:- 1423:- 1423:- 1423:- CH00 1448:- 1448:- 1448:- 1448:- CH00 1473:- 1473:- 1473:- 1473:- CH00 1498:- 1498:- 1498:- 1498:- CH00 1523:- 1523:- 1523:- 1523:- 0x10 > limit of 0xF for RecEnDelay_dq. Returning STATUS_LIMIT Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- ClkCh0 00 00 00 00 -- 01 09 - 3 - 1 -- 0201 ClkCh0 00 00 01 00 -- 01 09 - 3 - 1 -- 0201 ClkCh0 00 00 02 00 -- 01 09 - 3 - 1 -- 0201 ClkCh0 00 00 03 00 -- 01 09 - 3 - 1 -- 0201 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- ClkCh1 00 00 00 00 -- 01 09 - 3 - 1 -- 0201 ClkCh1 00 00 01 00 -- 01 09 - 3 - 1 -- 0201 ClkCh1 00 00 02 00 -- 01 09 - 3 - 1 -- 0201 ClkCh1 00 00 03 00 -- 01 09 - 3 - 1 -- 0201 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdCh0 00 00 00 00 -- 00 06 - 3 - 0 -- 0102 CmdCh0 00 00 01 00 -- 00 06 - 3 - 0 -- 0102 CmdCh0 00 00 02 00 -- 00 06 - 3 - 0 -- 0102 CmdCh0 00 00 03 00 -- 00 06 - 3 - 0 -- 0102 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdCh1 00 00 00 00 -- 01 09 - 3 - 1 -- 0201 CmdCh1 00 00 01 00 -- 01 09 - 3 - 1 -- 0201 CmdCh1 00 00 02 00 -- 01 09 - 3 - 1 -- 0201 CmdCh1 00 00 03 00 -- 01 09 - 3 - 1 -- 0201 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlCh0 00 00 00 00 -- 00 04 - 3 - 0 -- 0100 CtlCh0 00 00 01 00 -- 00 04 - 3 - 0 -- 0100 CtlCh0 00 00 02 00 -- 00 04 - 3 - 0 -- 0100 CtlCh0 00 00 03 00 -- 00 04 - 3 - 0 -- 0100 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlCh1 00 00 00 00 -- 01 07 - 3 - 1 -- 0199 CtlCh1 00 00 01 00 -- 01 07 - 3 - 1 -- 0199 CtlCh1 00 00 02 00 -- 01 07 - 3 - 1 -- 0199 CtlCh1 00 00 03 00 -- 01 07 - 3 - 1 -- 0199 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly -------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsNDelay_dq 00 00 00 00 -- -- 47 - - - - -- 0047 RxDqsNDelay_dq 00 00 01 00 -- -- 47 - - - - -- 0047 RxDqsNDelay_dq 00 00 02 00 -- -- 47 - - - - -- 0047 RxDqsNDelay_dq 00 00 03 00 -- -- 47 - - - - -- 0047 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly -------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsPDelay_dq 00 00 00 00 -- -- 47 - - - - -- 0047 RxDqsPDelay_dq 00 00 01 00 -- -- 47 - - - - -- 0047 RxDqsPDelay_dq 00 00 02 00 -- -- 47 - - - - -- 0047 RxDqsPDelay_dq 00 00 03 00 -- -- 47 - - - - -- 0047 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ---------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDelay_Actual 00 00 00 00 14 03 51 - 0 - 3 -- 0339 TxDqDelay_Actual 00 00 01 00 14 03 51 - 0 - 3 -- 0339 TxDqDelay_Actual 00 00 02 00 14 03 51 - 0 - 3 -- 0339 TxDqDelay_Actual 00 00 03 00 14 03 51 - 0 - 3 -- 0339 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly --------- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDrive 00 00 00 00 14 01 51 - 3 - 1 -- 0147 TxDqDrive 00 00 01 00 14 01 51 - 3 - 1 -- 0147 TxDqDrive 00 00 02 00 14 01 51 - 3 - 1 -- 0147 TxDqDrive 00 00 03 00 14 01 51 - 3 - 1 -- 0147 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqsDelay_dq 00 00 00 00 14 01 04 - 3 - 1 -- 0196 TxDqsDelay_dq 00 00 01 00 14 01 04 - 3 - 1 -- 0196 TxDqsDelay_dq 00 00 02 00 14 01 04 - 3 - 1 -- 0196 TxDqsDelay_dq 00 00 03 00 14 01 04 - 3 - 1 -- 0196 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly ------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- RecEnDelay_dq 00 00 00 00 17 15 83 - 2 - 15 -- 1523 RecEnDelay_dq 00 00 01 00 17 15 83 - 2 - 15 -- 1523 RecEnDelay_dq 00 00 02 00 17 15 83 - 2 - 15 -- 1523 RecEnDelay_dq 00 00 03 00 17 15 83 - 2 - 15 -- 1523 Signal CH RK ST HZ 192 96 1 M CC0 CC1 CC2 Vref Dly -------------- -- -- -- -- --- --- --- - --- --- --- ---- ---- RecEnPiCode_dq 00 00 00 00 -- -- 83 - - - - -- 0083 RecEnPiCode_dq 00 00 01 00 -- -- 83 - - - - -- 0083 RecEnPiCode_dq 00 00 02 00 -- -- 83 - - - - -- 0083 RecEnPiCode_dq 00 00 03 00 -- -- 83 - - - - -- 0083 CP 0xA5, Status[0] In a Dead Loop: Acting Dead!