Generalize synopsys dwc2 #1163
Generalize synopsys dwc2 #1163
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pi cm4 enumerated as full speed device
…t calibration. still has issue with gd32 with msc (does work with running with rtt as log).
merge GG12 GG12 to simply OPT_MCU_EFM32GG
…when setup recieved and control out data complete
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somehow the example (cdc_msc) does not work with latest broadcom peripherals since commit I have tried poking around and making modification where I think it could help. It seems usb phy is initialized but IRQ is not triggered. This proves to be too much knowledge for me digest. |
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From what I can tell this is a caching issue, not an interrupt one. The first gig of memory is marked as cachable now. If I change it to non-cacheable then the problem goes away. Does the DWC write to or read from any memory directly? It would need to be invalidated or cleaned if so. diff --git a/broadcom/mmu.c b/broadcom/mmu.c
index 098c728..3eefaac 100644
--- a/broadcom/mmu.c
+++ b/broadcom/mmu.c
@@ -24,7 +24,7 @@ void setup_mmu_flat_map(void) {
for (uint64_t i = 1; i < 512 - 8; i++) {
level_2_0x0_0000_0000_to_0x0_4000_0000[i] = (0x0000000000000000 + (i << 21)) |
MM_DESCRIPTOR_EXECUTE_NEVER |
- MM_DESCRIPTOR_MAIR_INDEX(MT_READONLY) |
+ MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
MM_DESCRIPTOR_INNER_SHAREABLE |
MM_DESCRIPTOR_ACCESS_FLAG |
MM_DESCRIPTOR_BLOCK | |
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thanks @tannewt for looking into this, I thought of the cache as well, did a quick check but didn't see any shared memory between cpu and usb. I could miss something, will poke more at that direction. thanks for looking into this 👍 👍 |
…t_enable90 also add hwcfg_list for reference
this get usb irq triggered even without ISB() in previous commit
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Thanks to Scott hint, I have narrowed it down to
It probably needs more efforts and knowledge to understand the reason behind this, for now I am happy with adding ISB() to dwc2_dcd_int_enable(). since the PRs has been quite lengthy with lots of commits. We should merge it now and come back to this later if it is an issue. |
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| TU_ATTR_ALWAYS_INLINE | ||
| static inline void dwc2_dcd_int_enable(uint8_t rhport) | ||
| { | ||
| (void) rhport; | ||
| BP_EnableIRQ(USB_IRQn); | ||
| __asm__ volatile("isb"); |
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mentioned in #1163 (comment)
| // Timer 1/1024 second tick | ||
| SYSTMR->CS_b.M1 = 1; | ||
| SYSTMR->C1 = SYSTMR->CLO + 977; | ||
| BP_EnableIRQ(TIMER_1_IRQn); |
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mentioned in #1163 (comment)
Describe the PR
Generalize Synopsys DWC2 driver. New driver is at
synopsys/dwc2For the time being, application can still pick the existing driver e.g st/synopsys/dcd_synopsys.c for stm32. Using this generalized driver is user choice until proven reliably.MCUs that use DWC2
Ref: linux driver for dwc https://github.com/torvalds/linux/tree/master/drivers/usb/dwc2