|
| 1 | +/* |
| 2 | + ******************************************************************************* |
| 3 | + * Copyright (c) 2020, STMicroelectronics |
| 4 | + * All rights reserved. |
| 5 | + * |
| 6 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 7 | + * the "License"; You may not use this file except in compliance with the |
| 8 | + * License. You may obtain a copy of the License at: |
| 9 | + * opensource.org/licenses/BSD-3-Clause |
| 10 | + * |
| 11 | + ******************************************************************************* |
| 12 | + * Automatically generated from STM32F103V(F-G)Tx.xml |
| 13 | + */ |
| 14 | +#include "Arduino.h" |
| 15 | +#include "PeripheralPins.h" |
| 16 | + |
| 17 | +/* ===== |
| 18 | + * Note: Commented lines are alternative possibilities which are not used per default. |
| 19 | + * If you change them, you will have to know what you do |
| 20 | + * ===== |
| 21 | + */ |
| 22 | + |
| 23 | +//*** ADC *** |
| 24 | + |
| 25 | +#ifdef HAL_ADC_MODULE_ENABLED |
| 26 | +WEAK const PinMap PinMap_ADC[] = { |
| 27 | + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 |
| 28 | +//{PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 |
| 29 | +//{PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 |
| 30 | + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 |
| 31 | +//{PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 |
| 32 | +//{PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 |
| 33 | + {NC, NP, 0} |
| 34 | +}; |
| 35 | +#endif |
| 36 | + |
| 37 | +//*** DAC *** |
| 38 | + |
| 39 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 40 | +#ifdef HAL_DAC_MODULE_ENABLED |
| 41 | +WEAK const PinMap PinMap_DAC[] = { |
| 42 | +//{PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 |
| 43 | +//{PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 |
| 44 | + {NC, NP, 0} |
| 45 | +}; |
| 46 | +#endif |
| 47 | +#endif |
| 48 | + |
| 49 | +//*** I2C *** |
| 50 | + |
| 51 | +#ifdef HAL_I2C_MODULE_ENABLED |
| 52 | +WEAK const PinMap PinMap_I2C_SDA[] = { |
| 53 | + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, AFIO_NONE)}, |
| 54 | + {NC, NP, 0} |
| 55 | +}; |
| 56 | + |
| 57 | +WEAK const PinMap PinMap_I2C_SCL[] = { |
| 58 | + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, AFIO_NONE)}, |
| 59 | + {NC, NP, 0} |
| 60 | +}; |
| 61 | +#endif |
| 62 | + |
| 63 | +//*** PWM *** |
| 64 | + |
| 65 | +#ifdef HAL_TIM_MODULE_ENABLED |
| 66 | +WEAK const PinMap PinMap_PWM[] = { |
| 67 | +#if 0 |
| 68 | + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1 |
| 69 | + //{PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1 |
| 70 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 71 | + //{PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM5_CH1 |
| 72 | +#endif |
| 73 | + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM2_CH2 |
| 74 | + //{PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2 |
| 75 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 76 | + //{PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM5_CH2 |
| 77 | +#endif |
| 78 | + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM2_CH3 |
| 79 | + //{PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3 |
| 80 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 81 | + //{PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM5_CH3 |
| 82 | +#endif |
| 83 | +#ifdef STM32F103xG |
| 84 | + //{PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM9_CH1 |
| 85 | +#endif |
| 86 | + //{PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4 |
| 87 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 88 | + //{PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM2_CH4 |
| 89 | + {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM5_CH4 |
| 90 | +#else |
| 91 | + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM2_CH4 |
| 92 | +#endif |
| 93 | +#if defined(STM32F103xG) |
| 94 | + //{PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM9_CH2 |
| 95 | +#endif |
| 96 | + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM3_CH1 |
| 97 | +#if defined(STM32F103xG) |
| 98 | + //{PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM13_CH1 |
| 99 | +#endif |
| 100 | + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N |
| 101 | + //{PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM3_CH2 |
| 102 | + //{PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 1)}, // TIM8_CH1N |
| 103 | +#if defined(STM32F103xG) |
| 104 | + //{PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM14_CH1 |
| 105 | +#endif |
| 106 | + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM1_CH1 |
| 107 | + //{PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1 |
| 108 | + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM1_CH2 |
| 109 | + //{PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2 |
| 110 | + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM1_CH3 |
| 111 | + //{PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3 |
| 112 | + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM1_CH4 |
| 113 | + //{PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4 |
| 114 | + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1 |
| 115 | + //{PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1 |
| 116 | + //{PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N |
| 117 | + {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM3_CH3 |
| 118 | + //{PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3 |
| 119 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 120 | + //{PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 1)}, // TIM8_CH2N |
| 121 | +#endif |
| 122 | + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N |
| 123 | + //{PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM3_CH4 |
| 124 | + //{PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4 |
| 125 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 126 | + //{PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 1)}, // TIM8_CH3N |
| 127 | +#endif |
| 128 | + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2 |
| 129 | + //{PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2 |
| 130 | + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1 |
| 131 | + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2 |
| 132 | + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM4_CH1 |
| 133 | + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM4_CH2 |
| 134 | + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM4_CH3 |
| 135 | +#if defined(STM32F103xG) |
| 136 | + //{PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM10_CH1 |
| 137 | +#endif |
| 138 | + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM4_CH4 |
| 139 | +#if defined(STM32F103xG) |
| 140 | + //{PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM11_CH1 |
| 141 | +#endif |
| 142 | + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3 |
| 143 | + //{PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3 |
| 144 | + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4 |
| 145 | + //{PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4 |
| 146 | + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 1)}, // TIM1_CH1N |
| 147 | + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 1)}, // TIM1_CH2N |
| 148 | +#if defined(STM32F103xG) |
| 149 | + //{PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM12_CH1 |
| 150 | +#endif |
| 151 | + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 1)}, // TIM1_CH3N |
| 152 | +#if defined(STM32F103xG) |
| 153 | + //{PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM12_CH2 |
| 154 | +#endif |
| 155 | + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_ENABLE, 1, 0)}, // TIM3_CH1 |
| 156 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 157 | + //{PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM8_CH1 |
| 158 | +#endif |
| 159 | + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_ENABLE, 2, 0)}, // TIM3_CH2 |
| 160 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 161 | + //{PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 2, 0)}, // TIM8_CH2 |
| 162 | +#endif |
| 163 | + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_ENABLE, 3, 0)}, // TIM3_CH3 |
| 164 | + //{PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 3, 0)}, // TIM8_CH3 |
| 165 | + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM3_ENABLE, 4, 0)}, // TIM3_CH4 |
| 166 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 167 | + //{PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE, 4, 0)}, // TIM8_CH4 |
| 168 | +#endif |
| 169 | + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM4_ENABLE, 1, 0)}, // TIM4_CH1 |
| 170 | + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM4_ENABLE, 2, 0)}, // TIM4_CH2 |
| 171 | + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM4_ENABLE, 3, 0)}, // TIM4_CH3 |
| 172 | + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM4_ENABLE, 4, 0)}, // TIM4_CH4 |
| 173 | +#if defined(STM32F103xG) |
| 174 | + {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM9_ENABLE, 1, 0)}, // TIM9_CH1 |
| 175 | + {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM9_ENABLE, 2, 0)}, // TIM9_CH2 |
| 176 | +#endif |
| 177 | + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 1, 1)}, // TIM1_CH1N |
| 178 | + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 1, 0)}, // TIM1_CH1 |
| 179 | + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 2, 1)}, // TIM1_CH2N |
| 180 | + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 2, 0)}, // TIM1_CH2 |
| 181 | + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 3, 1)}, // TIM1_CH3N |
| 182 | + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 3, 0)}, // TIM1_CH3 |
| 183 | + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_TIM1_ENABLE, 4, 0)}, // TIM1_CH4 |
| 184 | +#endif // if 0 |
| 185 | + {NC, NP, 0} |
| 186 | +}; |
| 187 | +#endif |
| 188 | + |
| 189 | +//*** SERIAL *** |
| 190 | + |
| 191 | +#ifdef HAL_UART_MODULE_ENABLED |
| 192 | +WEAK const PinMap PinMap_UART_TX[] = { |
| 193 | + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 194 | + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 195 | +//{PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 196 | + {NC, NP, 0} |
| 197 | +}; |
| 198 | + |
| 199 | +WEAK const PinMap PinMap_UART_RX[] = { |
| 200 | + {PA_3, USART2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, AFIO_NONE)}, |
| 201 | + {PA_10, USART1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, AFIO_NONE)}, |
| 202 | +//{PB_11, USART3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, AFIO_NONE)}, |
| 203 | + {NC, NP, 0} |
| 204 | +}; |
| 205 | + |
| 206 | +WEAK const PinMap PinMap_UART_RTS[] = { |
| 207 | + {NC, NP, 0} |
| 208 | +}; |
| 209 | + |
| 210 | +WEAK const PinMap PinMap_UART_CTS[] = { |
| 211 | + {NC, NP, 0} |
| 212 | +}; |
| 213 | +#endif |
| 214 | + |
| 215 | +//*** SPI *** |
| 216 | + |
| 217 | +WEAK const PinMap PinMap_SPI_MOSI[] = { |
| 218 | + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 219 | +//{PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 220 | + {NC, NP, 0} |
| 221 | +}; |
| 222 | + |
| 223 | +WEAK const PinMap PinMap_SPI_MISO[] = { |
| 224 | + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 225 | +//{PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 226 | + {NC, NP, 0} |
| 227 | +}; |
| 228 | + |
| 229 | +WEAK const PinMap PinMap_SPI_SCLK[] = { |
| 230 | + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 231 | +//{PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 232 | + {NC, NP, 0} |
| 233 | +}; |
| 234 | + |
| 235 | +WEAK const PinMap PinMap_SPI_SSEL[] = { |
| 236 | +//{PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 237 | +//{PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, |
| 238 | + {NC, NP, 0} |
| 239 | +}; |
| 240 | + |
| 241 | +//*** No CAN *** |
| 242 | + |
| 243 | +#ifdef HAL_CAN_MODULE_ENABLED |
| 244 | +WEAK const PinMap PinMap_CAN_RD[] = { |
| 245 | + {NC, NP, 0} |
| 246 | +}; |
| 247 | + |
| 248 | +WEAK const PinMap PinMap_CAN_TD[] = { |
| 249 | + {NC, NP, 0} |
| 250 | +}; |
| 251 | +#endif |
| 252 | + |
| 253 | +//*** No ETHERNET *** |
| 254 | + |
| 255 | +//*** No QUADSPI *** |
| 256 | + |
| 257 | +//*** USB *** |
| 258 | + |
| 259 | +#ifdef HAL_PCD_MODULE_ENABLED |
| 260 | +WEAK const PinMap PinMap_USB[] = { |
| 261 | + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DM |
| 262 | + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DP |
| 263 | + {NC, NP, 0} |
| 264 | +}; |
| 265 | +#endif |
| 266 | + |
| 267 | +//*** No USB_OTG_FS *** |
| 268 | + |
| 269 | +//*** No USB_OTG_HS *** |
| 270 | + |
| 271 | +//*** SD *** |
| 272 | + |
| 273 | +#if defined(STM32F103xE) || defined(STM32F103xG) |
| 274 | +#ifdef HAL_SD_MODULE_ENABLED |
| 275 | +WEAK const PinMap PinMap_SD[] = { |
| 276 | +//{PB_8, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D4 |
| 277 | +//{PB_9, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D5 |
| 278 | +//{PC_6, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D6 |
| 279 | +//{PC_7, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D7 |
| 280 | + {PC_8, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D0 |
| 281 | + {PC_9, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D1 |
| 282 | + {PC_10, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D2 |
| 283 | + {PC_11, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, AFIO_NONE)}, // SDIO_D3 |
| 284 | + {PC_12, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)}, // SDIO_CK |
| 285 | + {PD_2, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)}, // SDIO_CMD |
| 286 | + {NC, NP, 0} |
| 287 | +}; |
| 288 | +#endif |
| 289 | +#endif |
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